The technical field relates to memory devices capable of calibrating write currents in order to compensate for temperature variations.
Magnetic Random Access Memory (MRAM) is a proposed type of non-volatile memory. MRAM devices allow faster data access than conventional storage devices such as hard drives. FIG. 1 illustrates a conventional MRAM memory array 10 having resistive memory cells 12 located at cross points of row conductors 14 and column conductors 16. Each memory cell 12 is capable of storing the binary states of xe2x80x9c1xe2x80x9d and xe2x80x9c0.xe2x80x9d
FIG. 2 illustrates a conventional MRAM memory cell 12. The memory cell 12 includes a pinned layer 24 and a free layer 18. The pinned layer 24 has a magnetization of fixed orientation, illustrated by the arrow 26. The magnetization of the free layer 18, illustrated by the bi-directional arrow 28, can be oriented in either of two directions along an xe2x80x9ceasy axisxe2x80x9d of the free layer 18. The magnetizations of the free layer 18 and the pinned layer 24 can be either xe2x80x9cparallelxe2x80x9d or xe2x80x9cantiparallelxe2x80x9d to one another. The two orientations correspond to the binary states of xe2x80x9c1xe2x80x9d and xe2x80x9c0,xe2x80x9d respectively. The free layer 18 and the pinned layer 24 are separated by an insulating tunnel barrier layer 20. The insulating tunnel barrier layer 20 allows quantum mechanical tunneling to occur between the free layer 18 and the pinned layer 24. The tunneling is electron spin dependent, making the resistance of the memory cell 12 a function of the relative orientations of the magnetizations of the free layer 18 and the pinned layer 24.
Each memory cell 12 in the memory array 10 can have its binary state changed by a write operation. Write currents Ix and Iy supplied to the row conductor 14 and the column conductor 16 crossing at a selected memory cell 12 switch the magnetization of the free layer 18 between parallel and antiparallel with the pinned layer 24. The current Iy passing through the column conductor 16 results in the magnetic field Hx, and the current Ix passing through the row conductor 14 results in the magnetic field Hy. The fields Hx and Hy combine to switch the magnetic orientation of the memory cell 12 from parallel-to-antiparallel. A current xe2x88x92Iy is applied along with the current Ix to switch the memory cell 12 back to parallel.
In order to switch the state of the memory cell 12 from parallel-to-antiparallel, and vice versa, the combined field resulting from +/xe2x88x92 Hx and Hy exceeds a critical switching field Hc of the memory cell 12. If Hx and Hy are too small, they will not switch the orientation of the selected memory cell 12. If either Hx or Hy is too large, memory cells 12 on the row conductor 14 or the column conductor 16 of the selected memory cell 12 may be switched by the action of either Hx or Hy acting alone. Memory cells 12 subjected to either Hx or Hy alone are referred to as xe2x80x9chalf-selectedxe2x80x9d memory cells.
A problem may arise in MRAM arrays because the operational modes of an MRAM array and operating ambient temperature changes may cause the temperature of the MRAM array to vary, which would cause the coercivities of the memory cells to change. A change in coercivity of the memory cells changes the critical switching field Hc, which in turn changes the fields Hx and Hy required to switch the state of the cells. Temperature-dependent changes in critical switching field Hc increase the likelihood that an entire row or column of half-selected memory cells will be programmed due to the action of Ix or Iy alone, or, the likelihood that the write currents Ix and Iy acting together will be insufficient to switch a selected memory cell.
According to a first embodiment, a memory device comprises a substrate, an array of memory cells disposed over the substrate, a plurality of first conductors, a plurality of second conductors, wherein the first conductors cross the second conductors at the memory cells, a first current source selectively coupled to the first conductors and capable of providing a first write current to selected first conductors, a second current source selectively coupled to the second conductors and capable of providing a second write current to selected second conductors, a controller for controlling the application of the first and second write currents to the array of memory cells, and a temperature sensor disposed in the memory device. The temperature sensor senses a temperature of the memory device, and data from the temperature sensor are used to update the first and second write currents according to the sensed temperature.
According to a second embodiment, a method of calibrating a memory device comprises detecting a temperature of the memory device, determining whether the temperature of the memory device has changed by a threshold value, and updating at least one write current value if the temperature of the memory device changes by the threshold value.
According to a third embodiment, a method of filling a table with write current values for use in a memory device comprises applying a first write current and a second write current to conductors crossing at a reference memory cell when the memory array is at a temperature, detecting a state of the reference memory cell, increasing the first write current and the second write current if the state of the reference memory cell does not change, repeating the above steps until the state of the reference memory cell changes from a first state to a second state, and storing the first write current value and the second write current value that cause the state of the reference memory cell to change, wherein the first and second write current values are associated with the temperature.
Other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying figures.